`ifndef XPIP_RTL_IF_SVH
`define XPIP_RTL_IF_SVH

///axi interface for ip4
interface xpip_axi_intf(input logic aclk);
  
  logic [WID_AXI_ID - 1:0] awid, arid, bid, rid;
  logic [WID_EX_DATA - 1:0] wdata, rdata, cddata;
  logic [WID_EX_ADDR - 1:0] awaddr, araddr, acaddr;
  
  ///write address channel
  logic [7:0] awlen;
  logic [3:0] awcache, awqos, awregion;
  logic [2:0] awsize, awprot, awsnoop;
  logic [1:0] awburst, awdomain, awbar;
  logic awvalid, awready, awlock;
  
  ///write data channel
  logic [BYTES_EX_DATA-1:0] wstrb;
  logic wlast, wvalid, wready;
  
  ///write response channel
  logic [1:0] bresp;
  logic bvalid, bready;
  
  ///read address channel
  logic [7:0] arlen;
  logic [3:0] arcache, arqos, arregion, arsnoop;
  logic [2:0] arsize, arprot;
  logic [1:0] arburst, ardomain, arbar;
  logic arvalid, arready, arlock;
  
  ///read data channel
  logic [3:0] rresp;
  logic rlast, rvalid, rready;
  
  ///ace snoop address channel
  logic acvalid, acready;
  logic[2:0] acprot;
  logic[3:0] acsnoop;
  
  ///ace snoop response channel
  logic crvalid, crready;
  logic [4:0] crresp;
  
  ///ace snoop data channel
  logic cdvalid, cdready, cdlast;
  
  ///ace additional read/write acknowledge signal
  logic rack, wack;
  
 	modport mst(
   	input aclk,
          awready,
          wready,
          bid, bresp, bvalid,
          arready,
          rid, rdata, rresp, rlast, rvalid,
          acaddr, acsnoop, acprot, acvalid,
          crready,
          cdready,
   	output awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot, awvalid, awqos, awregion, awsnoop, awbar, awdomain,
           wdata, wstrb, wlast, wvalid, 
           bready,
           arid, araddr, arlen, arsize, arburst, arlock, arcache, arprot, arvalid, arqos, arregion, arsnoop, arbar, ardomain,
           rready,
           acready, 
           crvalid, crresp,
           cdvalid, cddata, cdlast,
           rack, wack
   );
   
  modport slv(
   	input aclk,
          awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot, awvalid, awqos, awregion, awsnoop, awbar, awdomain,
          wdata, wstrb, wlast, wvalid, 
          bready,
          arid, araddr, arlen, arsize, arburst, arlock, arcache, arprot, arvalid, arqos, arregion, arsnoop, arbar, ardomain,
          rready,
          acready, 
          crvalid, crresp,
          cdvalid, cddata, cdlast,
          rack, wack,
   	output awready,
           wready,
           bid, bresp, bvalid,
           arready,
           acaddr, acsnoop, acprot, acvalid,
           crready,
           cdready
   );
endinterface

///wishbone interface for ip4
interface xpip_wb_intf(input logic aclk);

  logic [WID_EX_DATA - 1:0] data_i, data_o;
  logic [WID_EX_ADDR - 1:0] addr_i, addr_o;
  logic ack_i, err_i, cyc_o, we_o, stb_o;

	logic [1:0]bte_o;
	logic [BYTES_EX_DATA - 1:0]sel_o;
	logic [2:0]cti_o;
  
 	modport mst(
   	input aclk,
          data_i, addr_i, ack_i, err_i,
   	output data_o,
           addr_o,
           cyc_o, we_o, stb_o,
           bte_o, sel_o, cti_o
   );
   
  modport slv(
   	input data_o,
          addr_o,
          cyc_o, we_o, stb_o,
          bte_o, sel_o, cti_o,
   	output aclk,
           data_i, addr_i, ack_i, err_i
   );
endinterface

///ip4 internal interface

interface xpip_intf(input logic clk, rst_n);
  
  isu2dpu_s isu2dpu;
  dpu2isu_s dpu2isu;
  
  isu2rfu_s isu2rfu;
  
  isu2ifu_s isu2ifu;
  ifu2isu_s ifu2isu;
  
  isu2lsu_s isu2lsu;
  lsu2isu_s lsu2isu;
  
  exu2isu_s exu2isu;
  isu2exu_s isu2exu;
  
  lsu2dcu_s lsu2dcu;
  dcu2lsu_s dcu2lsu;
  
  dpu2lsu_s dpu2lsu;
  
  rfu2lsu_s rfu2lsu;
  lsu2rfu_s lsu2rfu;
  
  sau2isu_s sau2isu;
  isu2sau_s isu2sau;
  
  dcu2biu_s dcu2biu;
  biu2dcu_s biu2dcu;
  
  dcu2tlb_s dcu2tlb;
  tlb2dcu_s tlb2dcu;
  
  core_cfg_inf_s cfg;
  
 	modport isu(
   	input dpu2isu,
         	ifu2isu,
         	lsu2isu,
         	exu2isu,
         	sau2isu,
   	output isu2dpu,
           isu2rfu,
           isu2ifu,
           isu2lsu,
           isu2exu,
           isu2sau,
           cfg
  );
   
  modport rfu(
    input isu2rfu
///    output rfu2dpu
  );
   
  modport lsu(
    input isu2lsu,
          dcu2lsu,
          dpu2lsu,
          rfu2lsu,
          cfg,
    output lsu2isu,
           lsu2dcu,
           lsu2rfu
  );
  
  modport exu(
    input isu2exu,
    output exu2isu
  );

  modport dpu(
    input isu2dpu,
    output dpu2isu
  );

  modport ifu(
    input isu2ifu,
    output ifu2isu
  );

  modport dcu(
    input lsu2dcu,
          biu2dcu,
          tlb2dcu,
          cfg,
    output dcu2biu,
           dcu2tlb,
           dcu2lsu
  );
          
  //synopsys translate_off
  modport test_dr(
    output isu2dpu, dpu2isu, isu2rfu, isu2ifu, ifu2isu,
           isu2lsu, lsu2isu, exu2isu, isu2exu, dcu2lsu,
           lsu2dcu, dpu2lsu, rfu2lsu, lsu2rfu
  );

  modport test_mo(
    input isu2dpu, dpu2isu, isu2rfu, isu2ifu, ifu2isu,
          isu2lsu, lsu2isu, exu2isu, isu2exu, dcu2lsu,
          lsu2dcu, dpu2lsu, rfu2lsu, lsu2rfu
  );
      
  default clocking cb @(posedge clk);
    default input #1step output #1ns;
    input isu2dpu, dpu2isu, isu2rfu, isu2ifu, ifu2isu,
          isu2lsu, lsu2isu, exu2isu, isu2exu, dcu2lsu,
          lsu2dcu, dpu2lsu, rfu2lsu, lsu2rfu;
  endclocking
  //synopsys translate_on

endinterface

`endif
